UAI=ST, PCI=ST, PS=DISABLED, UEI=ST, SRI=ST, AS=DISABLED, RCL=NO_EMPTY_ASYNCHRONOU, UPI=ST, AAI=ST, HCH=RS, FRI=ST, UI=ST
USB status (host mode)
| UI | USB interrupt (USBINT) 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. |
| UEI | USB error interrupt (USBERRINT) 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. |
| PCI | Port change detect. 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. |
| FRI | Frame list roll-over 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6). |
| RESERVED | Reserved. |
| AAI | Interrupt on async advance 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. |
| RESERVED | Not used by the Host controller. |
| SRI | SOF received 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base. |
| RESERVED | Not used by the Host controller. |
| RESERVED | Reserved. |
| HCH | HCHalted 0 (RS): The RS bit in USBCMD is set to zero. Set by the host controller. 1 (HALT): The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error). |
| RCL | Reclamation 0 (NO_EMPTY_ASYNCHRONOU): No empty asynchronous schedule detected. 1 (EMPTY_ASYNCHRONOU): An empty asynchronous schedule is detected. Set by the host controller. |
| PS | Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0). 0 (DISABLED): The periodic schedule status is disabled. 1 (DISABLED): The periodic schedule status is enabled. |
| AS | Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0). 0 (DISABLED): Asynchronous schedule status is disabled. 1 (DISABLED): Asynchronous schedule status is enabled. |
| RESERVED | Not used on Host mode. |
| RESERVED | Reserved. |
| UAI | USB host asynchronous interrupt (USBHSTASYNCINT) 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. |
| UPI | USB host periodic interrupt (USBHSTPERINT) 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. |
| RESERVED | Reserved. |